1. Field of the Invention
The present invention relates to a phase shifter and a bit phase shifter using the same. This Patent Application claims priority based on Japanese Patent application No. 2007-021725. The disclosure of the Japanese Patent application is incorporated herein by reference.
2. Description of Related Art
The phased array technique has been used for special purposes such as a radar and is used in commercial products in recent years. Application of the technique is further considered to receive satellite broadcasting. A phase shifter is indispensable to use of the phased array technique. In accordance with extension of application fields of the phased array technique, a demand is increasing for an inexpensive phase shifter suitable for commercial products and a satisfactory phase shifter having excellent high-frequency performance and suitable for receiving satellite broadcasting. However, it is difficult in a conventional phase shifter to satisfy requirement for the inexpensive phase shifter and requirement for the phase shifter with excellent high-frequency performance.
As a switching type of phase shifter used in a microwave band, an HPFLPF (high pass filter and low pass filter) switching type of phase shifter, or a switched line type of phase shifter are known. Japanese Patent No. 2679331 (first conventional example) describes a representative example of the HPFLPF switching type of phase shifter, and Japanese Laid Open Patent Application (JP-A-Heisei 7-38304) (second conventional example) describes a representative example of the switched line type of phase shifters.
FIG. 1 is a circuit diagram of an HPFLPF switching type of phase shifter. Referring to FIG. 1, the HPFLPF switching type of phase shifter includes an input-side SPDT (single pole double throw) switch 100, an HPF (high pass filter) 110, an LPF (low pass filter) 112, and an output-side SPDT switch 102.
The input-side SPDT switch 100 has an FET (field effect transistor) F10 connected to a first signal path, and an FET F11 connected to a second signal path. In the input-side SPDT switch 100, control voltages are applied to a control terminal CON 10 and a control terminal CON11 in a complementary manner, respectively. That is, an OFF voltage is applied to the control terminal CON11 when an ON voltage is applied to the control terminal CON10, and the ON voltage is applied to the control terminal CON11 when the OFF voltage is applied to the control terminal CON10. Accordingly, the FET F11 is in an off state when the FET F10 in an on state, and the FET F11 is in an on state when the FET F10 is in an off state.
The output-side SPDT switch 102 has an FET F12 connected to the first signal path, and an FET F13 connected to the second signal path. In the output-side SPDT switch 102, control voltages are applied to a control terminal CON12 and a control terminal CON13 in a complementary manner, respectively. Since an OFF voltage is applied to the control terminal CON13 when an ON voltage is applied to the control terminal CON12, the FET F13 is in an off state when the FET F12 is in an on state. Moreover, the ON voltage is applied to the control terminal CON13 when the OFF voltage is applied to the control terminal CON12, so that the FET F13 is in an on state when the FET F12 is in an off state.
The same control voltages are applied to the control terminal CON10 of the input-side SPDT switch 100 and the control terminal CON12 of the output-side SPDT switch 102. Accordingly, the FET F12 of the output-side SPDT switch 102 is turned on when the FET F10 of the input-side SPDT switch 100 is turned on. At this time, the first signal path is selected. The same control voltages are also applied to the control terminal CON11 of the input-side SPDT switch 100 and the control terminal CON13 of the output-side SPDT switch 102. Accordingly, the FET F13 of the output-side SPDT switch 102 is turned on when the FET F11 of the input-side SPDT switch 100 is turned on, and in this case the second signal path is selected.
The HPF 110 is disposed in the first signal path. The HPF 110 has a shunt inductor L10 connected to a ground, and two series-connected capacitors C10 and C11 are disposed to put the inductor L10 between them. On the other hand, the LPF 112 is disposed in the second signal path. The LPF 112 has a shunt capacitor C12 connected to a ground, and two series-connected inductors L11 and L12 are disposed to put the capacitor C12 between them.
When the ON voltages are applied to the control terminal CON10 and the control terminal CON12, and when the OFF voltages are applied to the control terminal CON11 and the control terminal CON13, a signal is inputted from an input terminal IN10 and is outputted from an output terminal OUT10 via the HPF 110. At this time, the signal passes through the HPF 110, and thereby the phase is advanced. Meanwhile, when the OFF voltages are applied to the control terminal CON10 and the control terminal CON12, and when the ON voltages are applied to the control terminal CON11 and the control terminal CON13, the signal inputted from the input terminal IN10 is outputted from the output terminal OUT10 via the LPF 112. At this time, the signal passes through the LPF 112 and thereby its phase is delayed.
In the HPFLPF switching type of phase shifter, the signal path connected to the HPF 110 and the signal path connected to the LPF 112 are switched by the SPDT switches 100 and 102, so that a phase shift amount corresponding to a phase difference between the two signal paths can be obtained. An arbitrary phase shift amount can be obtained by selecting the capacitors C10, C11 and C12 and the inductors L10, L11 and L12 to constitute the HPF 110 and the LPF 112, respectively. In a designed frequency band, a phase is advanced on an HPF 110 side, and the phase is delayed on an LPF 112 side. For example, if it is designed so that the phase on the HPF 110 side is advanced by 22.5 degrees and the phase on the LPF 112 side is delayed by 22.5 degrees at the designed frequency band, a phase shift amount of 45 degrees can be obtained.
FIG. 2 is a block diagram showing a configuration of another conventional phase shifter which is generally called a switched line type of phase shifter. Referring to FIG. 2, the switched line type of phase shifter includes an input-side SPDT switch 104, a first transmission line 120, a second transmission line 122, and an output-side SPDT switch 106.
In FIG. 2, when ON voltages are applied to a control terminal CON14 and a control terminal CON16, and when OFF voltages are applied to a control terminal CON15 and a control terminal CON17, an FET F14 and an FET F16 are turned on, and an FET F15 and an FET F17 are turned off. At this time, a signal is inputted from an input terminal IN11 and is outputted from an output terminal OUT11 via the transmission line 120. Meanwhile, when the OFF voltages are applied to the control terminal CON14 and the control terminal CON16, and when the ON voltages are applied to the control terminal CON15 and the control terminal CON17, the FET F14 and the FET F16 are turned off, and the FET F15 and the FET F17 are turned on. At this time, the signal is inputted from the input terminal IN11 and is outputted from the output terminal OUT11 via the transmission line 122.
The signal paths are operationally switched through on/off control of the SPDT switches 104 and 106 in the same manner as in the circuit shown in FIG. 1. In the switched line type of phase shifter, a phase difference between the two signal paths can be obtained as a phase shift amount. The transmission lines 120 and 122 having different lengths are connected to the respective signal paths, and in this case, the difference between phases of the signals due to different line lengths is utilized. Since the both of the signal paths have phase delays, it is assumed that the transmission line 120 has a length to delay the phase by 10 degrees in the designed frequency band, and the transmission line 122 has a length to delay the phase by 55 degrees. At this time, the phase shift amount of 45 degrees can be obtained.
As described above, a pair of HPF 110 and LPF 112 is used in the HPFLPF switching type of phase shifter and a pair of the transmission lines 120 and 122 having different lengths is used in the switched line type of phase shifter. Other phase shifters used in a millimeter wave band include a known phase shifter described in Japanese Patent Application Publication (JP-A-Heisei 11-195960) (third conventional example). The phase shifter described in the third conventional example relates to a phase shifter in a millimeter wave band in which SPDT switch characteristics cannot be obtained, so that a signal switch is not used. Thus, it is different from phase shifters of the HPFLPF switching type and the switched line type used in a microwave band. It should be noted that since many quarter-lines (four lines at minimum) are used in the phase shifter in the third conventional example, a chip size is increased. Therefore, it is extremely difficult to fabricate an inexpensive phase shifter.
A phase shifter can be configured by using either one of the conventional phase shifters, i.e. the HPFLPF switching type of phase shifter or the switched line type of phase shifter, without having any problems in the most cases. However, problems arise depending on a specific frequency band to be used and a phase shift amount.
If the phase shift amount is made smaller in the HPFLPF switching type of phase shifter, a phase shift amount advanced in a HPF and a phase shift amount delayed in an LPF need to be made smaller. In order to decrease the phase shift amounts of the filters, capacitors and inductors to constitute the filters need to have small constants. The LPF is configured of the series of inductors and the shunt capacitor, in which constants of these elements are made smaller in case of decreasing the phase shift amount. However, it is not possible in the shunt capacitor to ignore effect of a parasitic inductance caused by extending a wiring pattern in a high frequency band. Therefore, it is difficult to use small capacitance of a shunt capacitor. In order to realize a small capacitance of the shunt capacitor, problems arise such as increase of factors to process variations and increase of a phase shift error. Accordingly, frequency characteristics need to be sacrificed to some extent in case of the HPFLPF switching type of phase shifter having a small phase shift amount for the high frequency band.
Meanwhile, in the case of the switched line type of phase shifter, a large difference in the line length is required for a large phase shift amount. Accordingly, there are drawbacks such as arrangement of a long transmission line and an increased chip size. As a result, the cost increases. An influence of the larger line difference on frequency characteristics of a phase shifter increases.
The above problems occur in both the HPFLPF type of phase shifter and the switched line type of phase shifter, when a phase shift amount is set to be 20 to 45 degrees in the frequency band of about 10 to 15 GHz. Therefore, either frequency characteristics or costs are sacrificed in the conventional phase shifters.